The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for a tightly-coupled context-aware irritator thread creation for verification of microprocessors.
Modern microprocessors have complex designs in terms of an underlying micro-architecture, such as superscalar execution, simultaneous multithreading (SMT), numerous cores packed into a single integrated circuit (IC) chip, or the like. Sharing of hardware resources in these micro-architectures occur at different levels within various micro-architectural buffers such as Level 1 (L1), Effective-to-Real-Address Translation (ERAT), Translation Lookaside Buffer (TLB), Load Miss Queue (LMQ), Load and Store reorder queues, issue queues, or the like, as well as in various execution unit areas shared among all threads of a same core. Generally, at the IC chip level, Level 2 (L2) and Level 3 (L3) caches tend to be dynamically shared among different cores on a same IC chip. There is also a complex coherency protocol to manage data integrity across accesses from multiple cores and across multiple chips.